What VHDL libraries to use for decimal modulus -

library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;  entity two_number_split     port ( number  : in  integer range 0 99;            position0 : out  std_logic_vector (3 downto 0);            position1 : out  std_logic_vector (3 downto 0)); end two_number_split;  architecture behavioral of two_number_split     signal pos0, pos1 : std_logic_vector(3 downto 0); begin     convert: process(number, pos0, pos1)     begin             pos1 <= number/10;             pos0 <= number mod 10;             position0 <= std_logic_vector(pos0);             position1 <= std_logic_vector(pos1);     end process convert;  end behavioral; 

errors:

error:hdlcompiler:1638 - "c:\users\xxx\documents\ss\ise_ex\seven_segment\two_numbers.vhd" line 19: found '0' definitions of operator "/", cannot determine exact overloaded matching definition "/" error:hdlcompiler:1638 - "c:\users\xxx\documents\ss\ise_ex\seven_segment\two_numbers.vhd" line 20: found '0' definitions of operator "mod", cannot determine exact overloaded matching definition "mod" 

i think using wrong libraries. suggestions?i have tried combinations of libraries listed above , not sure going on.

you can modify declarations of pos0 , pos1 integer type, calculate , convert them bcd representation.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity two_number_split     port (          number:     in   integer range 0 99;         position0:  out  std_logic_vector (3 downto 0);         position1:  out  std_logic_vector (3 downto 0)     ); end two_number_split;  architecture behavioral of two_number_split     signal pos0, pos1 : natural range 0 9; -- std_logic_vector(3 downto 0); begin     convert: process(number, pos0, pos1)     begin             pos1 <= number/10;             pos0 <= number mod 10;             position0 <= std_logic_vector(to_unsigned(pos0,position0'length));              -- <= std_logic_vector(pos0);             position1 <= std_logic_vector(to_unsigned(pos1,position1'length));             -- <= std_logic_vector(pos1);     end process convert;  end behavioral; 

it uses to_unsigned convert decimal digit values pos1 , pos0 unsignedarray types. returned unsigned array length specified second argument literal.

you use unsigned type position0 , position1 , save type conversions each assignment.

the idea here threefold: readability, using operator functions compatible left , right arguments return value, , use of integer multiplying operators being faster unsigned operators. unsigned operation implied natural range of number.

and example works:

but isn't particularly synthesis eligible - having 2 multiplying operators. should need synthesize please see convert 8bit binary number bcd in vhdl inspiration on how avoid 7 bit multiplying operators.