vhdl - Compilation error in Vivado -

i downloaded vivado free web pack , try simulate simple project this:

library ieee; use ieee.std_logic_1164.all; entity async_rs_trig     port ( r : in  std_logic;            s : in  std_logic;        q : out  std_logic;        nq : out  std_logic); end async_rs_trig; architecture async_rs_trig of async_rs_trig     signal bq,nbq : std_logic; begin     bq <= r nor nbq;     nbq<= s nor bq;     q   <= bq;     nq  <=  nbq; end async_rs_trig; 

when push run simulation vivado try compile code , receve error:

error: [xsim 43-3409] failed compile generated c file       xsim.dir/async_rs_trig_behav/obj/xsim_0.c. 

but code right, tried simulate empty architecture , receved same error. have fix it?

thank you! regards

please rename architecture 'rtl' or ever, don't use entity's name architecture name again.

reply comment 1:

the simulation uses 2 processes, in case of isim these are:

1. yourtestbench_isim_beh.exe
2. simulator gui (isimgui.exe)

your source files translated c source files, compiled , linked executable file. can run *.exe file in interactive, (tcl)batch or gui mode. if call *.exe -gui simulator gui gets launched , connects yourtestbench_isim_beh.exe via tcp (tcp based interprocess communication - ipc).

normally personal firewall should ask grant isimgui.exe permission connect @ port on localhost.

as using vivado , xsim, should grant connection permissions vivado's gui process.

this problem occur hardware server (hw_server).